Each year, John Cooley does a great job previewing the companies at DAC. From that list, here's the ones that sound interesting to me.
OneSpin's 360MV tool does something called "gap-detection" plus timing diagrams on your design's System Verilog Assertions. (booth 625)
Real Intent Meridian CDC for clock domain crossing verification. Formal analysis and interfaces to simulation.
NuSym DeNibulator's intelligent testbench" It hunts down your hard to find coverage points and automatically tweaks your TB to reach them. It's next gen constrained random. (booth 379)
Certess Certitude testbench error injection.(booth 324)
Another "intelligent testbench" is Mentor inFact - graphical tool that generates, grades, and then upgrades TBs. It
now drives existing e, Vera, SV, or C/C++ TBs. Does OVM & VMM.(booth 2301)
CebaTech is showing their C2R Compiler,which takes untimed ANSI C and outputs Verilog RTL. (booth 760)
Forte Cynthesizer v3.4 (SystemC design) adds support for Power Compiler for "best-in-class area, performance, and now power results" and "management of ECOs by graphically mapping RTL back to the original SystemC design" and inter-block interfaces.(booth 1645)
Mentor 's Catapult C synth & Vista ESL tools. (booth 2301)
Carbon's Model Studio does Verilog-RTL-to-C conversion for simulation, to get early models for architectural work(booth 2467)
Synfora Pico Extreme C synthesis tool (booth 329)
Bluespec : "general purpose high-level synthesis & simulationfor modeling, verification and implementation". (booth 2367)
Imperas : yet-another-ISS tool, OVPsim, for embedded SW. (booth 467)
Mirabilis VisualSim does "graphical SystemC TLM 2.0 import without any code development; and power estimation of the full system." (booth 778)
Steve Golson's "Four Principles of Flow Engineering" DAC Tuesday at 10:30 AM, Room 206AB
Dassault Synchronicity DesignSync Cadence data management tools. (booth 620)
EVE ZeBu is showcasing PCIe and AXI synthesizable transactors and its System Verilog support for custom transactors.(booth 301)
Mentor Veloce "using mixed System Verilog and SystemC based upon System Verilog DPI standard 2.0" with Nucleus embedded RTOS (booth 2301)
Synfora Pico Extreme FPGA (booth 329)
VeriEZ EZVerify covers you design, assertions and testbench, with added full System Verilog support this year plus VMM/OVM checking (booth 1936)
Veritools usually has linters, code coverage and waveform viewers. Supports SV dynamic objects. (booth 1334)
Denali PureSpec System Verilog methodology support (OVM,VMM, AVM) in all IP blocks. (booth 1611)
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