I haven't been to the Design Automation Conference (DAC) for several years. Last time I was there, SystemC was the hot new language on the block, ready to revolutionise the design and verification world. In the intervening years, the hype has died down a bit and SystemC has settled into a comfortable niche as a solid option for doing higher level modeling, that previously was done in a roll your own C or C++ environment. The features for modeling parallelism and communication along with structure are good enough to mean you don't need to do it all from scratch. The speed is slowly getting better, but it isn't going to change the design world. It somewhat dropped the ball by being implemented as a set of library extensions to C++, rather than an enclosed language (which would have had the potential at least to be synthesisable - something SpecC got right).
Now several years later, the hot new language on the block, ready to revolutionise the design and verification world is SystemVerilog. Low level enough to write hardware. Feature rich enough to support verification. An IEEE standard (that nobody quite implements). All things to all people. Maybe. Or maybe 3 distinct languages that happen to run together on one simulator - which seems closer to the reality. A step in the right direction perhaps, and certainly the current flavour of the month. OVM and VMM (verification libraries built on top of SystemVerilog) are the thing that kept coming up time and again as I looked through the DAC sessions, with an eye towards verification and system-level design. With the news that the VMM is open source, along with the already freely available OVM, perhaps the opportunity to merge to one set of libraries across the big three has some potential, if we ignore all the legacy investment that will still need to be supported.
These are the sessions that caught my eye at this year's DAC and that I hope to attend. I'm surprised quite how many of them overlap, so I suspect I'll be missing more than I might like. There is so much going on this year! I plan on blogging throughout the conference and sharing the interesting things I find.
Monday 9th June
Find the Toughest Bugs with Mentor Graphics 0-In Formal Verification
Migrating to OVM for Multi-Language Verification
Gary Smith on EDA: Trends and What's Hot at DAC
Real World Advantages of the OSCI TLM-2.0 Standard for Model Interoperability and IP Reuse
Tuesday 10th June
Catapult & Vista: Integrating ESL Synthesis & Verification
Experiences and Advances in Formal and Dynamic Verification
Formal Verification Technology
Innovation in Verification Luncheon
Multi-processor SoCs: The Next Generation
iDesign II - practical aspects of using SystemVerilog
Wednesday 11th June
Getting Real With OVM, A True Open Source Verification Standard
Challenges on Design Complexities for Advanced Wireless Silicon Systems
Verifying Really Complex Systems: On Earth and Beyond
Wild and Crazy Ideas
Thursday 12th June
Advances in Verification of Abstract (pre-RTL) Models
Closing the Loop in Intelligent Testbench Automation
Your Functional Verification Roadmap: OVM, VMM, or Roll Your Own?
Formal Verification: Dude or Dud? Experiences from the Trenches
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